EW31244SL7QV Datasheet, PDF (199/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 116. SU PCI DPA Interrupt Pending Register - SUPDIPR (Sheet 5 of 5)
PCI
Attributes
31
28
24
20
16
12
8
4
0
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
DPA Mode BAR0 Offset
000H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
SATA Port 0 PHY Change State Interrupt - When set, the PHY either went from READY to
NOT-READY, or from NOT-READY to READY. The source of this interrupt is from bit 16 (DIAG_N) of
the SError register. This interrupt is cleared by writing a 1 to bit 16 of the SError register. Refer to
00
0₂
Section 5.10.12.2, “SU PCI DPA SATA SError Register - SUPDSSER” on page 222.
The default value after reset is 0₂, for example the PHY will not be ready. When the PHY becomes
ready (state change from not-ready to ready) as part of the initialization sequence, the value will change
to 1₂.
Developer’s Manual
April 2004
199