EW31244SL7QV Datasheet, PDF (228/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.6 SU PCI DPA BIST FIS Control and Status Register - SUPDBFCSR
The SU PCI DPA BIST Control and Status Register is a 32-bit register. This register may be used
to send a BIST Activate FIS to a far-end device. It may also be used to receive a BIST Activate FIS
from a far-end device. A far-end device may be placed in one of three modes: Retimed loopback
mode, AFE Analog loopback mode, and Transmit-Only mode. Refer to the Serial ATA
Specification.
Table 140.
The BIST generator and data checker has 4 built-in patterns to be used in far-end retimed mode
only. The first three modes are single patterns repeated indefinitely. The frame counter is not used
for these patterns. The error will freeze at FFFFh if that many errors are detected. This prevents
false interpretations due to a counter rollover. The BIST pattern 3 will send a counting pattern. The
errors are not detected until three consecutive counts are detected. If this synchronization is never
reached, then the error counter will contain 0. The frame counter will increment falsely if the
pattern FFFFh is received. This test was designed to characterize a mostly working SATA physical
connection. For such excessive error rates as would cause no three consecutive counting pattern
Dwords to be recognized correctly, this feature should not be relied upon.
SU PCI DPA BIST FIS Control and Status Register - SUPDBFCSR (Sheet 1 of 3)
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rv rv rw rw rw rv rv rv rv rv rv rw ro ro ro ro ro ro ro rw rw rw rw rw rw rw rw rw
PCI IDE Mode Offset
= 044H,
Bit
Default
31:30
00₂
29:28
00₂
27
0₂
26
0₂
25
0₂
24
0₂
23
0₂
22
0₂
21
0₂
DPA Mode Offset
Port 0 = 344H, Port 1 = 544H
Port 2 = 744H, Port 3 = 944H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Description
BIST Pattern Select. These bits select the BIST pattern to generate for far-end loopback testing. The
pattern is generated by setting bit 23 of this register.
00₂ - D21.5s
01₂ - D24.3s
10₂ - 3(D10.2s) and K28.5
11₂ - Counting pattern with smart comparison.
BIST Check Selection. Should be set to the same value as BIST pattern Select (bits [31:30]). Setting
with a different value will cause mismatch.
Force a transmit side disparity error. Errors will be forced for the duration of this bit being set.
Force receive side disparity error. Errors will be forced for the duration of this bit being set.
Clear the BIST Errors/Frames registers. Writing a 1 to this bit will clear the BIST Errors register and
BIST Frames register. This bit is always read as a 0.
BIST Check Enable. This bit enables the checker to compare the incoming loopback data stream
selected by bits [29:28]. This bit must be set to 1 for proper BIST operation. When this bit is not set, the
incoming data stream will not be verified.
BIST Pattern Enable. This bit enables the pattern generation selected by bits [31:30]. Note that sending
a BIST Activate FIS does not automatically enables the generation of the BIST patterns. Write to 1 to
enable and 0 to disable.
Invert Encoder outputs (effectively inverts tx +/-).
Invert Decoder inputs (effectively inverts rx +/-)
228
April 2004
Developer’s Manual