EW31244SL7QV Datasheet, PDF (41/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Serial EEPROM
3.1.7 CHIP_ERASE Command
Figure 12.
As an alternative to the SECT_ERASE, the CHIP_ERASE command will erase every byte in all
sectors that are not write protected. First, the device must be write enabled through the WREN
command, then the CHIP ERASE command may be executed. The CHIP_ERASE command is
internally controlled; it will automatically be timed to completion. The CHIP_ERASE cycle time
typically is 3.5 seconds.
During the internal erase cycle, all commands will be ignored except RDSR. The EEPROM will
automatically return to the write disable state at the completion of the CHIP_ERASE cycle. The
chip erase (CHIP_ERASE) operation is shown in Figure 12.
Chip Erase (CHIP_ERASE) Operation
SCS#
SCLK
SDO
01234567
01100010
SDI
Hi -Z
The CHIP_ERASE command may only be issued when the EEPROM is ready to accept a new
command. When the device is busy, it cannot accept any new commands except RDSR. To issue a
RDID command:
1. Issue a WREN command as described in Section 3.1.5.
2. Issue a RDSR command to read that the RDY# bit is LOW and the WEN bit is HIGH in the
EEPROM’s Status Register to ensure that the EEPROM is ready to receive a write command.
3. When RDY# is not low, continue issuing RDSR commands until RDY# becomes low.
4. Issue the CHIP_ERASE command with an 8-bit write of 62h to the SPI Command Register at
offset 90h.
Developer’s Manual
April 2004
41