EW31244SL7QV Datasheet, PDF (102/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.9
Message-Signaled Interrupts
The GD31244 controller may deliver interrupt to the Host Processor through the P_INTA# output
pin or the Message Signaled Interrupt (MSI) mechanism.
When a host processor enables Message-Signaled Interrupts (MSI) on the GD31244 controller, a SATA
Unit interrupt will be signaled to the host through a PCI write instead of the assertion of the P_INTA#
output pin.
PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a states: “PCI-X devices that generate
interrupts are required to support message-signaled interrupts, as defined by the PCI Local Bus
Specification, Revision 2.2 and must support a 64-bit message address.” “Devices that require interrupts in
systems that do not support message-signaled interrupts, must implement interrupt pins.” Thus, the
GD31244 controller needs to implement both wired and message-signaled interrupt delivery mechanisms.
In support of MSI, the GD31244 controller will implement the MSI capability structure. The
capability structure includes the “SU MSI Message Control Register - SUMSI_Message_Control”
on page 162, the “SU MSI Message Address Register - SUMSI_Message_Address” on page 163,
the “SU MSI Message Upper Address Register - SUMSI_Message_Upper_Address” on page 164
and the“SU MSI Message Data Register - SUMSI_Message_Data” on page 165.
During system initialization, the configuration software for an MSI system will read the Message
Control Register to determine that the GD31244 controller supports a 64-bit Message Address, and
that it is capable of generating four unique interrupt messages.
After gathering this data from all of the MSI capable devices in the system, the configuration
software will decide where to initialize the Message Address and how many unique messages each
MSI capable device is allowed. Then, software will write the Message Address Registers (and the
Message Upper Address Registers when Message Address is above the 4G address boundary¹),
and the Message Data Register. This system specified data will be used to route the interrupt
request message to the appropriate entry in a host processor Local APIC table.
Configuration of MSI completes with a write to the Message Control Register which includes an
update to the Multiple Message Enable field and the MSI enable bit of each device. This will inform
the device how many unique messages (Local APIC table entries) have been allocated for exclusive
use by that device and enable that device for MSI. Device hardware is required to handle allocation of
fewer unique interrupt messages than requested by the Multiple Message Capable field.
The GD31244 controller may generate up to four messages - one per SATA port, but it is also able
to generate less than four messages - two or one message. Interrupt handler software needs to read
the SATA port status and interrupt pending registers to determine the cause of the interrupt when
more than one SATA ports are represented by less than four MSI messages.
Note: When host software enables MSI, the interrupt will not result in the assertion of the P_INTA#
output pin.
5.9.1
Level-Triggered Versus Edge-Triggered Interrupts
When MSI is disabled, the P_INTA# pin remains asserted and pended to the host when any of the
SATA Unit interrupt sources requires service. Since the PCI pin signaled interrupt is level-triggered,
the interrupt service routine will not drop out of the service routine until the interrupt signal is
deasserted. This will ensure that an interrupt will not be missed.
MSI interrupts are inherently edge-triggered, in that an interrupt is only pended to the host as a
write event when any of the SATA Port requires service.
1. When host software writes the Message Upper address register to a non-zero value, device hardware will use a write transaction with a Dual
Address Cycle (DAC) to present the full 64-bit address to the bus.
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April 2004
Developer’s Manual