EW31244SL7QV Datasheet, PDF (73/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Table 27. SATA Superset Registers for SATA Port 0 in DPA Mode
31
0
Offset
SU PCI DPA SATA SStatus Register - SUPDSSSR
300H
SCRs
Registers
SU PCI DPA SATA SError Register - SUPDSSER
SU PCI DPA SATA SControl Register - SUPDSSCR
SU PCI DPA Set Device Bits Register - SUPDSDBR
304H
308H
30CH
Reserved
310H - 33FH
SU PCI DPA PHY Feature Register - SUPDPFR
340H
SU PCI DPA BIST FIS Control and Status Register - SUPDBFCSR
344H
SU PCI DPA BIST Errors Register - SUPDBER
348H
BIST
Registers
SU PCI DPA BIST Frames Register - SUPDBFR
SU PCI DPA Host BIST Data Low Register - SUPDHBDLR
SU PCI DPA Host BIST Data High Register - SUPDHBDHR
34CH
350H
354H
SU PCI DPA Device BIST Data Low Register - SUPDDBDLR
358H
SU PCI DPA Device BIST Data High Register - SUPDDBDHR
35CH
SU PCI DPA Queuing Table Address Register Low - SUPDQTBARL
360H
SU PCI DPA Queuing Table Address Register High - SUPDQTBARH
364H
SU PCI DPA DMA Setup FIS Control and Status Register - SUPDDSFCSR
368H
SU PCI DPA Host DMA Buffer Identifier Low Register - SUPDHDBILR
36CH
SU PCI DPA Host DMA Buffer Identifier High Register - SUPDHDBIHR
370H
SU PCI DPA Host Reserved DWORD Register 0 - SUPDHRDR0
374H
DMA Setup
Registers
SU PCI DPA Host DMA Buffer Offset Register - SUPDHDBOR
SU PCI DPA Host DMA Transfer Count Register - SUPDHDTCR
SU PCI DPA Host Reserved DWORD Register 1- SUPDHRDR1
378H
37CH
380H
SU PCI DPA Device DMA Buffer Identifier Low Register - SUPDDDBILR
384H
SU PCI DPA Device DMA Buffer Identifier High Register - SUPDDDBIHR
388H
SU PCI DPA Host Reserved DWORD Register 0 - SUPDHRDR0
38CH
SU PCI DPA Device DMA Buffer Offset Register - SUPDDDBOR
390H
SU PCI DPA Device DMA Transfer Count Register - SUPDDDTCR
394H
SU PCI DPA Device Reserved DWORD Register 1 - SUPDDRDR1
398H
Reserved
39CH
Reserved
3A0H
Reserved
3A4H
Reserved
3A8H
Reserved
3ACH
Reserved
Route
Reserved
Reserved
3B0H
3B4H
Reserved
3B8H
Reserved
3BCH
Reserved
3C0H
Reserved
3C4H
Reserved
3C8H
Test Register 0
3CCH
Test Register 1
3D0H
Reserved
3D4H - 3FFH
NOTE: The Offsets mentioned above, only indicate Port 0. To view the other three Port offset values, see each specific register.
Developer’s Manual
April 2004
73