EW31244SL7QV Datasheet, PDF (184/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.6
Table 112.
SU PCI DPA Mode Registers
This section defines the SATA Unit registers as viewed from the PCI bus when in Direct Port
Access mode. The registers are memory-mapped into the PCI memory space.
Every PCI device/function implements its own separate configuration address space and
configuration registers. The PCI Local Bus Specification, Revision 2.2 requires that configuration
space be 256 bytes, and the first 64 bytes must adhere to a predefined header format.
Refer to Section 5.10.1, “PCI IDE Mode Registers” on page 103 for the configuration space, as the
configuration registers are the same as in the PCI IDE mode. There are a few registers that are
different that are highlighted in this section.
When in the Direct Port Access mode, the Serial ATA Unit registers are mapped into the PCI
memory space. Only one 64-bit Base Address Register is defined to access all four SATA port
registers. Table 112 shows the differences in the configuration space between the two modes.
The SATA Port registers are listed in Table 113. When in Direct Port Access mode, SU PCI DPA
Base Address Register 0 - SUDBAR0 and SU PCI DPA Upper Base Address Register 0 -
SUPDUBAR0, are used to access the SATA port registers.
Configuration Space Comparison
In PCI IDE Mode
In Direct Port Access Mode
SU Base Address Register 0 - SUBAR0 SU PCI DPA Base Address Register 0 - SUDBAR0
SU Base Address Register 1 - SUBAR1
SU PCI DPA Upper Base Address Register 0 -
SUPDUBAR0
SU Base Address Register 2 - SUBAR2 Reserved
SU Base Address Register 3 - SUBAR3 Reserved
SU Base Address Register 4 - SUBAR4 Reserved
SU Base Address Register 5 - SUBAR5 Reserved
Offset
10H
14H
18H
1CH
20H
24H
184
April 2004
Developer’s Manual