EW31244SL7QV Datasheet, PDF (77/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.4
Reset Initialization
When the PCI bus reset signal P_RST# is asserted, the GD31244 controller:
• resets all internal units
• resets all the registers to their default values
• latches the configuration strap on the rising edge of P_RST#.
• latches P_REQ64# to determine the PCI bus width
• initiates a COMRESET/hardware reset to the SATA devices on the rising edge of P_RST#.
Note that COMRESET is initiated only when in PCI IDE mode. When in DPA mode,
COMRESET have to be explicitly initiated using the SControl Register by software. Refer to
the DET field in the “SU PCI DPA SATA SControl Register - SUPDSSCR” on page 225.
All the state machines on the GD31244 controller get reset upon the assertion of the PCI bus signal
P_RST#. In addition, all the registers on the GD31244 controller get initialized to their default
values.
Upon the deassertion of P_RST#, the GD31244 controller samples the DPA_MODE# strap pin to
set the operating mode. When DPA_MODE# is high after reset is deasserted, the GD31244
controller will present itself on the PCI bus as a PCI IDE device (Default Mode). When
DPA_MODE# is low after reset, the GD31244 controller will present itself on the PCI bus in DPA
(Direct Port Access) mode (requires a pull-down resistor).
The P_REQ64# signal is also sampled to determine when the GD31244 controller is connected on a
64-bit PCI bus. P_REQ64# is latched on the rising edge of P_RST#. The state of P_REQ64# at the
rising edge of P_RST# notifies the GD31244 controller that it is connected to a 64-bit or 32-bit PCI
bus.
The 32BITPCI# is also sampled to indicate the width of the PCI-X bus to the PCI-X Status
Register. When 32BITPCI# is low after reset is deasserted, it implies a 32-bit PCI-X Bus (requires
pull-down resistor). When 32BITPCI# high after reset is deasserted, it implies a 64-bit PCI-X Bus
(Default mode)
A COMRESET is used to hardware reset the SATA device and also to initialize the serial bus
communication link. A COMRESET is issued differently in PCI mode and DPA mode. In PCI IDE
mode, upon the deassertion of P_RST#, a COMRESET is issued to each SATA drive. In DPA mode,
the serial bus will stay offline after P_RST# is deasserted. Software must intervene in order to initiate
a COMRESET initialization sequence using the SControl register. Refer to the “SU PCI DPA SATA
SControl Register - SUPDSSCR” on page 225. This is done in order to minimize an initial power
supply current draw due to multiple spindles starting at once.
A COMRESET sequence causes a hardware reset of the SATA device and initialization of the serial
bus communication link. Because of the nature of the Serial ATA bus, before the SATA port may
communicate to the attached SATA device, an initialization sequence is required to establish the
communication link. The PHY internally provides a mechanism (PHY Ready) to indicate that a
device is present. Until a device is not detected the Command Block Status register returns a 7FH
value when read. This value is consistent with ATA standard devices, which indicates that a device is
not connected and therefore, software should not try writing to the taskfile registers. After the device
is detected, the Status register returns an 80H value. Bit 7 set (BSY bit) indicates that a device is
present but is busy performing its initialization sequence. After the device completes its initialization
sequence, it will send a Register FIS to initialize the taskfile registers. The values returned in the
Register FIS are device dependent, and provide the status of the drive. The Error register contains a
diagnostic code. The Sector Count, Sector Number, Cylinder Low, Cylinder High and Device/Head
Developer’s Manual
April 2004
77