EW31244SL7QV Datasheet, PDF (103/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10 Register Definitions
The section is broken into three subsections. Each subsection describes a different programming
interface.
• PCI IDE Mode Registers
• Direct Port Access Mode Registers
5.10.1 PCI IDE Mode Registers
This section defines the SATA port registers as viewed from the PCI bus when in PCI IDE mode
Every PCI device/function implements its own separate configuration address space and
configuration registers. The PCI Local Bus Specification, Revision 2.2 requires that configuration
space be 256 bytes, and the first 64 bytes must adhere to a predefined header format.
Figure 32 defines the header format. Table 35 shows the PCI configuration registers. Table 35
shows the entire Serial ATA Unit configuration space (including header and extended registers) and
the corresponding section that describes each register.
Figure 32. SU in PCI IDE Mode Interface Configuration Header Format
BIST
Device ID
Status
Class Code
Header Type
Vendor ID
Command
Revision ID
Latency Timer
Cacheline Size
00H
04H
08H
0CH
Subsystem ID
Base Address 0
Base Address 1
Base Address 2
Base Address 3
Base Address 4
Base Address 5
Reserved
Subsystem Vendor ID
10H
14H
18H
1CH
20H
24H
28H
2CH
Maximum Latency
Expansion ROM Base Address
Reserved
Reserved
Minimum Grant
Interrupt Pin
Capabilities Pointer
Interrupt Line
30H
34H
38H
3CH
The Serial ATA Unit is programmed through a Type 0 configuration command on the PCI
interface. Serial ATA Unit (SU) configuration space is function number zero.
Beyond the required 64-byte header format, Serial ATA Unit configuration space implements
extended register space in support of the unit functionality. Refer to the PCI Local Bus
Specification, Revision 2.2 for details on accessing and programming configuration register space.
Developer’s Manual
April 2004
103