EW31244SL7QV Datasheet, PDF (244/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.20 SU PCI DPA Host DMA Transfer Count Register - SUPDHDTCR
Table 154.
The SU PCI DPA Host DMA Transfer Count Register is the fifth DWORD parameter of the SATA
DMA Setup Host-to-Device FIS. Refer to the Serial ATA Specification.
SU PCI DPA Host DMA Transfer Count Register - SUPDHDTCR
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
PCI IDE Mode Offset
= 07CH,
DPA Mode Offset
Port 0 = 37CH, Port 1 = 57CH
Port 2 = 77CH, Port 3 = 97CH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
31:00 0000_0000H Transfer Count - This is the number of bytes that will be read or written by the device.
244
April 2004
Developer’s Manual