EW31244SL7QV Datasheet, PDF (68/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
Figure 22.
Figure 22 shows how the SATA port registers are mapped in native-PCI IDE mode. Note that the DMA
Controller Registers for both channels are accessed using the Base Address Register at offset 20H.
SATA Unit Register Mapping in Native-PCI Mode
Offset PCI Configuration Space
10H
14H
18H
1CH
20H
24H
Base Address Register 0
Base Address Register 1
Base Address Register 2
Base Address Register 3
Base Address Register 4
Base Address Register 5
Channel 0
Command Block Registers
Control Bock Registers
Channel 1
Command Block Registers
Control Bock Registers
Channel 0 & Channel 1
DMA Registers
SATA Superset Registers
68
April 2004
Developer’s Manual