EW31244SL7QV Datasheet, PDF (100/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.8
SATA Port Interrupt Generation
When the SATA Unit on the GD31244 controller is in PCI IDE mode, interrupts that are generated
follow the ATA standard. An ATA device generates an interrupt using the INTRQ hardware signal
during normal data transfer to indicate data transfer completion and/or to indicate an error condition. An
error condition is indicated when the ERR bit (bit 0) in the Status register is set. In contrast, a SATA
device indicates an interrupt by using the ‘I’ bit (a pseudo INTRQ signal) in the PIO Setup FIS, or the
Device-to-Host Register FIS. A hardware interrupt is then generated based on the ‘I’ being set.
When the SATA Unit operates in PCI DPA Mode, interrupts may also be generated by bits being
set in the SATA SError Registers, in addition to the normal ATA standard interrupts explained
above. Refer to Table 136, “SU PCI DPA SATA SError Register - SUPDSSER” on page 222, and
Table 116, “SU PCI DPA Interrupt Pending Register - SUPDIPR” on page 194.
The block diagram in Figure 31 shows how each SATA Unit generates and posts interrupts coming
from the SATA ports. SATA Unit posted interrupts are routed onto PCI interrupt line - PINTA#.
Interrupts may also be generated using Message-Signaled Interrupts. Refer to Section 5.9,
“Message-Signaled Interrupts” on page 102. When MSI is enabled, the GD31244 controller will
not generate interrupts using the interrupt line - PINTA#.
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April 2004
Developer’s Manual