EW31244SL7QV Datasheet, PDF (153/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.44 SU PCI-X Command Register - SUPCIXCMD
Table 82.
This register controls various modes and features of SATA Unit when operating in the PCI-X
mode.
SU PCI-X Command Register - SUPCIXCMD
PCI
Attributes
15
12
8
4
0
rv rv rv rv rv rv rv rv rv rw rw rw rw rw rw rw
PCI Configuration Offset
E2H - E3H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
15:7 000000000₂ Reserved.
Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions
the device is permitted to have outstanding at one time.
Register Maximum Outstanding
0
1
1
2
6:4
011₂
2
3
3
4
4
8
5
12
6
16
7
32
Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when
initiating a Sequence with one of the burst memory read commands.
Register Maximum Byte Count
3:2
00₂
0
1
512
1024
2
2048
3
4096
Enable Relaxed Ordering - When this bit is set the GD31244 controller will set the relaxed ordering bit in
1
1₂
the Requester Attributes of Transactions it initiates. Note that this bit does not have any effect on MSI
transactions, as an MSI transaction is not permitted to set the relaxed ordering bit in its attributes.
Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to
recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts
0
0₂
P_SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set.
NOTE: This bit has no effect when the GD31244 controller encounters a data parity error when
mastering an MSI transaction.
Developer’s Manual
April 2004
153