EW31244SL7QV Datasheet, PDF (19/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
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Table 2.
Terms and Definitions (Sheet 2 of 2)
Term
Definition
PLL Phase Lock Loop
PLL
This block is used to synchronize an internal clocking reference so that the input
high-speed data stream may be properly decoded
PRD Physical Region Description
Prepreg
Material used for the lamination process of manufacturing PCBs. It consists of a
layer of epoxy material that i placed between two cores. This layer melts into
epoxy layer of epoxy material that i placed between two cores. This layer melts
into epoxy when heated and forms around adjacent traces.
QWORD 64-bit data word.
RDID Read Manufacturer and Product ID
RDSR Read Status Register
RX This is a receiver port contains the basic high-speed receiver electronics.
RX + / RX - Inbound high-speed differential signals connected to the serial ATA cable.
RxData
10b encoding Serially encoded 10b data attached to the high-speed serial
differential line receiver. The 8B/10B encoding scheme transmits eight bits as a
10-bit code group. This encoding is used with Gigabit Ethernet, Fibre Channel and
InfiniBand.
SATA Serial ATA
SECT Sector
SERR# SERR is the System Error Signal on the PCI bus.
SPI Serial Peripheral Interface. SPI is used to access the GD31244 EEPROM.
Stub Branch from a trunk terminating at the pad of an agent.
Terminate the high-speed serial cable. This block is used to synchronize an
Termination Calibration internal clocking reference so that the input high-speed data stream may be
properly decoded.
TX This is a transmit port that contains the basic high-speed driver electronics.
TX + / TX - Outbound high-speed differential signals connected to the serial ATA cable.
TxData Serially encoded 10b data attached to the high-speed serial differential line driver.
Upstream At or toward a PCI bus with a lower number (after configuration).
WEN Write Enable
WPEN Write Protection Enable
WRDI Reset Write Enable Latch
WREN Write Enable
WRSR Write Status Register
Developer’s Manual
April 2004
19