EW31244SL7QV Datasheet, PDF (208/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.9.6
Table 123.
SU PCI DPA Cylinder Low Register - SUPDCLR
The SU PCI DPA Cylinder Low Register is a 16-bit read/write register. The content of the SU PCI
DPA Cylinder Low Register is a command parameter. The content of this register must be loaded
before the SU PCI DPA Command Register is written. The content of the SU PCI DPA Cylinder
Low Register is command dependent. Refer to the AT Attachment with Packet Interface-6
(ATA/ATAPI-6) Specification.
SU PCI DPA Cylinder Low Register - SUPDCLR
PCI
Attributes
15
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
DPA Mode BAR0 Offset
Port 0 = 210H, Port 1 = 410H
Port 2 = 610H, Port 3 = 810H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
15:00
Cylinder Low/LBA Mid - This field is dependent on the device access methods. There are three method:
Device
Dependent ^a
• CHS addressing: This field indicates the lower cylinder byte to request as part of the
Cylinder/Head/Sector format.
• 28-bit LBA addressing: This lower eight bits of this field is used for bit positions LBA[15:8] of the
28-bit address LBA[27:0].
• 48-bit LBA addressing: This upper and lower bytes of this field is used for bit positions LBA[39:32]
and LBA[15:8] respectively of the 48-bit addressing LBA[47:0].
a. After a hardware reset, software reset, or an EXECUTE DEVICE DIAGNOSTIC command, the device will return a signature value. The signature
value is device dependent. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification.
208
April 2004
Developer’s Manual