EW31244SL7QV Datasheet, PDF (127/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.19 SU Expansion ROM Base Address Register - SUEXROMBAR
The internal ROM controller performs an auto-detect function at the end of reset. If the external
device is not detected, all bits in this register are LOW, effectively disabling the ROM memory
space. This register conforms to the PCI spec for the expansion ROM interface. A read following a
write of FFFF FFFEh will return FFFE 0000h. This hardwired value indicates the presence of an
external 128K x 8 Serial EEPROM. Firmware then writes a base address in bits [31:17] and the
LSB is set to enable accesses. The ROM can then be accessed with PCI/PCI-X 32-bit memory
transactions to the 128K byte space starting at the base address. The expansion ROM interface
disconnects from data transfer after the first data phase of a burst read transaction, so burst
transactions are valid but do not burst. Reads are performed through this port without the use of the
SPI Configuration Registers. Writes are also performed through this port, but require proper use of
the SPI Configuration Register.In PCI IDE mode, the superset registers begins at offset 00H
relative to this Base Address Register.
Table 57.
The interface supports DWORD, word and byte accesses for both read and write transactions. The
serial EEPROM device is an ST Microelectronics M25P10 or an Atmel AT25F1024. The
EEPROM device’s SPI registers can be accessed via the PCI configuration space (at 90h and 94h)
and provides write enable, status, and erase commands. The device is read directly using the
address of this BAR without having to use the SPI registers.
SU Expansion ROM Base Address Register - SUEXROMBAR
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv rv rv rv rv rv rv rw
PCI Configuration Address Offset
30H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:17
16:
00
Default
Description
0000_0000H Base address to access 128K x 8 ROM memory space..
0000h ROM Size Supported - 128 Kbytes (per PCI Specification)
0/1
ROM Space enable. Set to 1 to enable access. The reset value is 0h if an external EEPROM is not
detected at power-up. The reset value is 1h if an external EEPROM is detected.
Developer’s Manual
April 2004
127