EW31244SL7QV Datasheet, PDF (46/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Serial EEPROM
3.1.9.3 SPI Data Register - Address 94h
Table 20.
3.1.10
SPI Data Register - Address 94h
Master / Slave Mode and Direct Port Access Mode
Bits
31:16
15:8
7:0
7
6
5
4
3
2
1
0
Type
r/-
r/-
r/-
r/w
Reset
0
00h
00h
00h
Description
Reserved.
Device ID for the RDID command.
Manufacturer’s ID for the RDID command.
WPEN
Reserved
Reserved
Reserved
BP1
BP0
WEN
RDYn
External WPB pin override
Block Protect 1
Block Protect 0
Write Enable
Ready Active LOW
This is a multifunction register used by three commands. For the RDID command, it is a read-only
register with the Manufacturer’s ID and Device ID in the upper and lower bytes respectively. For
the WRSR/RDSR commands, the lower byte is a write/read register with the bit definitions
presented in Table 20. The WPEN command is not applicable if the serial EEPROM device has its
write protect pin WPB inactive high. Refer to the serial EEPROM device specification for how to
use these bits.
Detection of the EEPROM at Power-Up
Immediately after power-on reset (an internal event based upon the power supply exceeding a
minimum voltage), the GD31244 reads the EEPROM through the SPI interface to determine if an
EEPROM is present.
46
April 2004
Developer’s Manual