EW31244SL7QV Datasheet, PDF (122/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.14 SU Base Address Register 3 - SUBAR3
Table 52.
The SU Base Address Register 3 (SUBAR3) defines the base I/O address of the Control Block
Registers for Channel 1.
SU Base Address Register 3 - SUBAR3
PCI
Attributes
31
28
24
20
16
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rv ro
PCI Configuration Address Offset
1CH - 1FH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
31:04
03:02
01
00
Default
Description
0000_037H
Base Address 3 - These bits define the base address of the Control Block Registers in PCI I/O space for
channel 1.
01₂
Base Address 3 - These bits define the base address of the Control Block Registers in PCI I/O space for
channel 1.
0₂
Reserved.
1₂
I/O Space Indicator - This bit field describes memory or I/O space base address. The SATA Unit in PCI
IDE mode is mapped into I/O space, thus this bit must be one.
122
April 2004
Developer’s Manual