EW31244SL7QV Datasheet, PDF (21/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Overview
Intel^® 31244 PCI-X to Serial ATA Controller
Overview
2
Figure 1.
The Intel^® 31244 PCI-X to Serial ATA Controller (GD31244) is a single-chip solution for a PCI-X
to Serial ATA Controller. It accepts host commands through the PCI-X bus, processes them and
transmits them to one of four Serial ATA targets. The GD31244 supports Serial ATA speeds of
1.5 Gbits/s of 8b/10b encoded data which is equivalent to 150 Mbytes/s of raw data. The GD31244
derives its Serial ATA clocks from an internal PLL with a reference clock of 37.5 MHz. On the
64-bit PCI-X bus, when run at the maximum frequency of 133 MHz, the GD31244 supports a
maximum burst transfer rate of 1064 Mbytes/s.
The GD31244 controller may be used to build standalone PCI-X HBA cards to interface Serial
ATA Disk Drives, CD-ROMs, DVD ROMs or Tape drives. The GD31244 is completely software
compatible with all existing operating systems which support ATA interfaces: Windows*,
Windows NT*, Linux*, Solaris*, Unix*, etc. In PC systems, the GD31244 may also be configured
to provide additional storage capacity to systems already supporting four ATA targets. In non-PC
systems, the GD31244 may be used as a generic storage controller in servers, RAID subsystems
and Network Attached Storage (NAS) systems. The ease-of-use, flexibility, performance and low
cost of the GD31244 make it an ideal choice for all of these applications.
In addition to PCI IDE mode, the GD31244 supports a new programming interface, referred to as
Direct Port Access Mode. In this new mode, the SATA ports are set up to operate independently,
for example no master/slave emulation is done as in PCI IDE mode. In this mode the SATA ports
registers are memory-mapped.
Intel^® 31244 PCI-X to Serial ATA Controller Block Diagram
AD[63:0]
CBE#[7:0]
PAR
PAR64
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
REQ#
REQ64#
ACK64#
GNT#
CLK
RST#
PERR#
SERR#
INTA#
IDSEL
PCI-X
Interface
EEPROM
SD0
SD1
SCLK
SCS#
FIFO
and DMA
Engine
FIFO
and DMA
Engine
FIFO
and DMA
Engine
FIFO
and DMA
Engine
Serial ATA
Transport/
Link Layer
OOB
Serial ATA
Transport/
Link Layer
OOB
Serial ATA
Transport/
Link Layer
OOB
Serial ATA
Transport/
Link Layer
OOB
Serializer
Deserializer
Serializer
Deserializer
Serializer
Deserializer
Serializer
Deserializer
TX0P
TX0N
RX1N
RX1P
TX1P
TX1N
RX1N
RX1P
TX2P
TX2N
RX2N
RX2P
TX3P
TX3N
RX3N
RX3P
B2843-01
Developer’s Manual
April 2004
21