EW31244SL7QV Datasheet, PDF (249/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.12.25 SU PCI DPA Device DMA Buffer Offset Register - SUPDDDBOR
Table 159.
The SU PCI DPA Device DMA Buffer Offset Register is the fourth DWORD parameter of the
SATA DMA Setup Device-to-Host FIS. Refer to the Serial ATA Specification.
SU PCI DPA Device DMA Buffer Offset Register - SUPDDDBOR
PCI
Attributes
31
28
24
20
16
12
8
4
0
ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro
PCI IDE Mode Offset
= 090H,
DPA Mode Offset
Port 0 = 390H, Port 1 = 590H
Port 2 = 790H, Port 3 = 990H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
Bit
31:00
Default
Description
0000_0000H Buffer Offset - The buffer offset field of the First Party Setup FIS.
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Developer’s Manual
April 2004
249