EW31244SL7QV Datasheet, PDF (206/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.9.4
Table 121.
SU PCI DPA Sector Count Register - SUPDSCR
The SU PCI DPA Sector Count Register is a 16-bit read/write register. The content of the SU PCI
DPA Sector Count Register is a command parameter. The content of this register must be loaded
before the SU PCI DPA Command Register is written. The content of the SU PCI DPA Sector
Count Register is command dependent. Refer to the AT Attachment with Packet Interface-6
(ATA/ATAPI-6) Specification.
SU PCI DPA Sector Count Register - SUPDSCR
PCI
Attributes
15
12
8
4
0
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
DPA Mode BAR0 Offset
Port 0 = 208H, Port 1 = 408H
Port 2 = 608H, Port 3 = 808H
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Bit
Default
Description
15:00
Sector Count/LBA Low:
Device
• CHS addressing - only the lower byte is used for specifying a sector count.
Dependent ^a _{• 28-bit LBA addressing - only the lower byte is used for specifying a sector count.}
• 48-bit LBA addressing - a 16-bit value is used for specifying a sector count.
a. After a hardware reset, software reset, or an EXECUTE DEVICE DIAGNOSTIC command, the device will return a signature value. The signature
value is device dependent. Refer to the AT Attachment with Packet Interface-6 (ATA/ATAPI-6) Specification.
206
April 2004
Developer’s Manual