EW31244SL7QV Datasheet, PDF (158/252 Pages) Intel Corporation – Intel® 31244 PCI-X to Serial ATA Controller

Intel^® 31244 PCI-X to Serial ATA Controller
Programming Interface
5.10.2.48 SU Power Management Capabilities Register - SUPMCR
Table 86.
Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management
Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides
information on the capabilities of the SATA Unit function related to power management.
SU Power Management Capabilities Register - SUPMCR
PCI
Attributes
15
12
8
4
0
ro ro ro ro ro ro ro ro ro ro ro rv ro ro ro ro
Bit
15:11
10
9
8:6
5
4
3
2:0
PCI Configuration Offset
EAH - EBH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Default
00000₂
0₂
0₂
000₂
1₂
0₂
0₂
010₂
Description
PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# is not
supported by the GD31244 controller.
D2_Support - This bit is set to 0₂ indicating that the GD31244 controller does not support the D2 Power
Management State
D1_Support - This bit is set to 0₂ indicating that the GD31244 controller does not support the D1 Power
Management State
Aux_Current - This field is set to 000₂ indicating that the GD31244 controller has no current
requirements for the 3.3Vaux signal as defined in the PCI Bus Power Management Interface
Specification, Revision 1.1
DSI - This field is set to 1₂ meaning that this function will require a device specific initialization sequence
following the transition to the D0 uninitialized state.
Reserved.
PME Clock - Since the GD31244 controller does not support PME# signal generation.
Version - Setting these bits to 010₂ means that this function complies with PCI Bus Power Management
Interface Specification, Revision 1.1
158
April 2004
Developer’s Manual