HD6417750 Datasheet, PDF (999/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Appendix C Mode Pin Settings
The MD8–MD0 pin values are input in the event of a power-on reset via the 5(6(7 or
SCK2/05(6(7 pin.
(1) Clock Modes
• Clock Operating Modes (SH7750, SH7750S)
External
Pin Combination
Frequency
(vs. Input Clock)
Clock
Operating
Mode
1/2
Frequency
MD2 MD1 MD0 Divider
Peripheral
CPU Bus Module
PLL1 PLL2 Clock Clock Clock
FRQCR
Initial Value
0
0
0
0
Off
On On 6
3/2 3/2
H'0E1A
1
1
Off
On On 6
1
1
H'0E23
2
1
0
On
On On 3
1
1/2
H'0E13
3
1
Off
On On 6
2
1
H'0E13
4
1
0
0
On
On On 3
3/2 3/4
H'0E0A
5
1
Off
On On 6
3
3/2
H'0E0A
Notes: 1. Turning on/off of the ½ frequency divider is solely determined by the clock operating
mode.
2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input
frequency (f ) and CKIO clock output (f ) in section 22.3.1, Clock and Control Signal
EX
OP
Timing.
• Clock Operating Modes (SH7750R)
Clock
Operating
Mode
External
Pin Combination
MD2 MD1 MD0
PLL1
CPU
PLL2 Clock
Frequency
(vs. Input Clock)
Bus Peripheral
Clock Module Clock
FRQCR
Initial Value
0
0
0
0
On (×12) On 12
3
3
H'0E1A
1
1
On (×12) On 12
3/2
3/2
H'0E2C
2
1
0
On (×6) On 6
2
1
H'0E13
3
1
On (×12) On 12
4
2
H'0E13
4
1
0
0
On (×6) On 6
3
3/2
H'0E0A
5
1
On (×12) On 12
6
3
H'0E0A
6
1
0
Off (×6) Off 1
1/2
1/2
H'0808
Notes: 1. The multiplication factor of PLL 1 is solely determined by the clock operating mode.
2. For the ranges of input clock frequency, see the descriptions of the EXTAL clock input
frequency (f ) and CKIO clock output (f ) in section 22.3.1, Clock and Control Signal
EX
OP
Timing.
Rev. 6.0, 07/02, page 947 of 986