HD6417750 Datasheet, PDF (403/1039 Pages) Renesas Technology Corp – SuperH RISC engine

13.2.7 Wait Control Register 3 (WCR3)
Wait control register 3 (WCR3) is a 32-bit readable/writable register that specifies the cycles
inserted in the setup time from the address until assertion of the write strobe, and the data hold
time from negation of the strobe, for each area. This enables low-speed memory to be connected
without using external circuitry.
WCR3 is initialized to H'07777777 by a power-on reset, but is not initialized by a manual reset or
in standby mode.
Bit: 31
30
29
28
27
26
25
24
Bit name: —
—
—
—
—
A6S0 A6H1 A6H0
Initial value: 0
0
0
0
0
1
1
1
R/W: R
R
R
R
R
R/W R/W R/W
Bit: 23
Bit name: —
Initial value: 0
R/W: R
22
A5S0
1
R/W
21
A5H1
1
R/W
20
A5H0
1
R/W
19
A4RDH*
0
R/W*
18
A4S0
1
R/W
17
A4H1
1
R/W
16
A4H0
1
R/W
Bit: 15
14
13
12
11
10
9
8
Bit name: —
A3S0 A3H1 A3H0
—
A2S0 A2H1 A2H0
Initial value: 0
1
1
1
0
1
1
1
R/W: R
R/W R/W R/W
R
R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: A1RDH* A1S0 A1H1 A0H0
—
A0S0 A0H1 A0H0
Initial value: 0
1
1
1
0
1
1
1
R/W: R/W* R/W R/W R/W
R
R/W R/W R/W
Note: * SH7750R only
Bits 31 to 27, 23, 19*, 15, 11, 7*, and 3—Reserved: These bits are always read as 0, and should
only be written with 0.
Note: * SH7750R only
Rev. 6.0, 07/02, page 351 of 986