HD6417750 Datasheet, PDF (17/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Section
19.2.4 Interrupt Exception
Handling and Priority
Page
758
759 to
761
19.3.1 Interrupt Priority
762
Registers A to D (IPRA–
IPRD)
19.3.3 Interrupt-Priority-Level 764
Setting Register 00
(INTPRI00)
19.3.4 Interrupt Source
765
Register 00 (INTREQ00)
(SH7750R Only)
19.3.5 Interrupt Mask
766
Register 00 (INTMSK00)
(SH7750R Only)
19.3.6 Interrupt Mask Clear 767
Register 00 (INTMSKCLR00)
(SH7750R Only)
19.3.7 Bit Assignments of 767
INTREQ00, INTMSK00, and
INTMSKCLR00 (SH7750R
Only)
19.4.1 Interrupt Operation 768
Sequence
19.5 Interrupt Response
771
Time
20.2.4 Break Address Mask 778, 779
Register (BAMRA)
20.2.10 Break Data Mask 783
Register B (BDMRB)
20.3.7 Program Counter
791
(PC) Value Saved
20.4 User Break Debug
794
Support Function
21.1.1 Features
799
21.1.2 Block Diagram
800
Item
Description
Description added
Table 19.5 Interrupt
Description added to
Exception Handling Sources table, Notes added and
and Priority Order
amended
Table 19.6 Interrupt Request SH7750R added to
Sources and IPRA–IPRD
Note 3
Registers
Newly added
Newly added
Newly added
Newly added
19.3.4 moved to 19.3.7
Note 3 added
Note amended
Bit 2, and Bits 3, 1, and 0
Description added
Bits 31 to 0
Description added
20.3.7 Program Counter
(PC) Value Saved
Figure 20.2 User Break
Debug Support Function
Flowchart
Figure 21.1 Block Diagram
of H-UDI Circuit
4. Description added
Amended
Description amended
Figure changed and
Note added
Rev. 6.0, 07/02, page xv of I