HD6417750 Datasheet, PDF (159/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Examples of RAM usage with the SH7750R is shown below.
• In SH7750/SH7750S-compatible mode (CCR.EMODE = 0)
H'7C00 0000 to H'7C00 1FFF (8 kB): RAM area (entries 256 to 511)
H'7C00 2000 to H'7C00 3FFF (8 kB): RAM area (entries 256 to 511)
:
:
:
In the same pattern, shadows of the RAM area are created in 8-kbyte blocks until H'7FFF
FFFF is reached.
• In double-sized cache mode (CCR.EMODE = 1)
In this mode, the 8 kbytes comprising entries 256 to 511 of OC way 0 are designated as RAM
area 1 and the 8-kbytes comprising entries 256 to 511 of OC way 1 are designated as RAM
area 2.
H'7C00 0000 to H'7C00 1FFF (8 kB): Corresponds to RAM area 1
H'7C00 2000 to H'7C00 3FFF (8 kB): Corresponds to RAM area 2
H'7C00 4000 to H'7C00 5FFF (8 kB): Corresponds to RAM area 1
H'7C00 6000 to H'7C00 7FFF (8 kB): Corresponds to RAM area 2
:
:
:
In the same pattern, shadows of the RAM area are created in 16-kbyte blocks until H'7FFF
FFFF is reached.
4.3.7 OC Index Mode
Setting CCR.OIX to 1 enables OC indexing to be performed using bit [25] of the effective
address. This is called OC index mode. In normal mode, with CCR.OIX cleared to 0, OC indexing
is performed using bits [13:5] of the effective address. Using index mode allows the OC to be
handled as two areas by means of effective address bit [25], providing efficient use of the cache.
The SH7750R cannot be used in RAM mode when OC index mode is selected.
4.3.8 Coherency between Cache and External Memory
Coherency between cache and external memory should be assured by software. In the SH7750
Series, the following four new instructions are supported for cache operations. Details of these
instructions are given in the Programming Manual.
Invalidate instruction:
Purge instruction:
Write-back instruction:
Allocate instruction:
OCBI @Rn
OCBP @Rn
OCBWB @Rn
MOVCA.L R0,@Rn
Cache invalidation (no write-back)
Cache invalidation (with write-back)
Cache write-back
Cache allocation
Rev. 6.0, 07/02, page 107 of 986