HD6417750 Datasheet, PDF (222/1039 Pages) Renesas Technology Corp – SuperH RISC engine

These possibilities are shown in the individual instruction descriptions. All exception events
that originate in the FPU are assigned as the same exception event. The meaning of an
exception is determined by software by reading system register FPSCR and interpreting the
information it contains. If no bits are set in the cause field of FPSCR when one or more of bits
O, U, I, and V (in case of FTRV only) are set in the enable field, this indicates that an actual
exception source is not generated. Also, the destination register is not changed by any enable
exception handling operation.
Except for the above, the FPU disables exception handling. In all processing, the bit
corresponding to source V, Z, O, U, or I is set to 1, and disable exception handling is provided
for each exception.
 Invalid operation (V): qNAN is generated as the result.
 Division by zero (Z): Infinity with the same sign as the unrounded value is generated.
 Overflow (O):
When rounding mode = RZ, the maximum normalized number, with the same sign as the
unrounded value, is generated.
When rounding mode = RN, infinity with the same sign as the unrounded value is
generated.
 Underflow (U):
When FPSCR.DN = 0, a denormalized number with the same sign as the unrounded value,
or zero with the same sign as the unrounded value, is generated.
When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated.
 Inexact exception (I): An inexact result is generated.
6.6 Graphics Support Functions
The SH7750 Series supports two kinds of graphics functions: new instructions for geometric
operations, and pair single-precision transfer instructions that enable high-speed data transfer.
6.6.1 Geometric Operation Instructions
Geometric operation instructions perform approximate-value computations. To enable high-speed
computation with a minimum of hardware, the SH7750 Series ignores comparatively small values
in the partial computation results of four multiplications. Consequently, the error shown below is
produced in the result of the computation:
Maximum error = MAX (individual multiplication result ×
2 ) + MAX (result value × 2 , 2 ) ^{–MIN (number of multiplier significant digits–1, number of multiplicand significant digits–1)}
–23 –149
The number of significant digits is 24 for a normalized number and 23 for a denormalized number
(number of leading zeros in the fractional part).
Rev. 6.0, 07/02, page 170 of 986