HD6417750 Datasheet, PDF (539/1039 Pages) Renesas Technology Corp – SuperH RISC engine

13.3.16 Notes on Usage
Refresh: Auto refresh operations stop when a transition is made to standby mode, hardware
standby mode or deep-sleep mode. If the memory system requires refresh operations, set the
memory in the self-refresh state prior to making the transition to standby mode, hardware standby
mode or deep-sleep mode.
Bus Arbitration: On transition to standby mode or deep-sleep mode, the processor in master
mode does not release bus privileges. In systems performing bus arbitration, make the transition to
standby mode or deep-sleep mode only after setting the bus privilege release enable bit
(BCR1.BREQEN) to 0 for the processor in master mode. If the bus privilege release enable bit
remains set to 1, operation cannot be guaranteed when the transition is made to standby mode or
deep-sleep mode.
Synchronous DRAM Mode Register Setting (SH7750, SH7750S Only): The following
conditions must be satisfied when setting the synchronous DRAM mode register.
• The DMAC must not be activated until synchronous DRAM mode register setting is
completed.*¹
• Register setting for the on-chip peripheral modules*² must not be performed until synchronous
DRAM mode register setting is completed.*³
Notes: *1 If a conflict occurs between synchronous DRAM mode register setting and memory
access using the DMAC, neither operation can be guaranteed.
*2 This applies to the following on-chip peripheral modules: CPG, RTC, INTC, TMU,
SCI, SCIF, and H-UDI.
*3 If synchronous DRAM mode register setting is performed immediately following write
access to the on-chip peripheral modules*², the values written to the on-chip peripheral
modules cannot be guaranteed.
Rev. 6.0, 07/02, page 487 of 986