HD6417750 Datasheet, PDF (681/1039 Pages) Renesas Technology Corp – SuperH RISC engine

1
Serial
data
Start
bit
0 D0
Data
Parity Stop Start
bit bit bit
Data
Parity Stop
bit bit
D1
D7 0/1 1 0 D0 D1
D7 0/1 1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
TXI interrupt
request
request
Data written to SCTDR1
and TDRE flag cleared to
0 by TXI interrupt handler
One frame
TEI interrupt
request
Figure 15.9 Example of Transmit Operation in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Serial Data Reception (Asynchronous Mode): Figure 15.10 shows a sample flowchart for serial
reception.
Use the following procedure for serial data reception after enabling the SCI for reception.
Rev. 6.0, 07/02, page 629 of 986