 English |
|
|
|
|
|
|
|
| HD6417750 Datasheet, PDF (930/1039 Pages) Renesas Technology Corp – SuperH RISC engine | |||
| |||
| ◁ |
CKIO
A25âA0
RD/
T1
Tw
T2
tAD
tCSD
tRWD
tRSD
tRSD
tAD
tCSD
tRWD
tRSD
D63âD0
(read)
tWED1
tWEDF
tRDS
tRDH
tWEDF
D63âD0
(write)
tWDD
tWDD
tBSD
tBSD
tWDD
tRDYS
tRDYH
DACKn
(SA: IO â memory)
DACKn
(SA: IO â memory)
tDACD
tDACDF
tDACD
DACKn
(DA)
tDACD
tDACD
tDACDF
tDACD
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.16 SRAM Bus Cycle: Basic Bus Cycle (One Internal Wait)
Rev. 6.0, 07/02, page 878 of 986
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese