HD6417750 Datasheet, PDF (57/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 1.1 SH7750 Series Features (cont)
Item
Features
Cache memory
• Instruction cache (IC)
[SH7750, SH7750S] _{ 8 kbytes, direct mapping}
 256 entries, 32-byte block length
 Normal mode (8-kbyte cache)
 Index mode
• Operand cache (OC)
 16 kbytes, direct mapping
 512 entries, 32-byte block length
 Normal mode (16-kbyte cache)
 Index mode
 RAM mode (8-kbyte cache + 8-kbyte RAM)
 Choice of write method (copy-back or write-through)
• Single-stage copy-back buffer, single-stage write-through buffer
• Cache memory contents can be accessed directly by address mapping
(usable as on-chip memory)
• Store queue (32 bytes × 2 entries)
Cache memory
[SH7750R]
• Instruction cache (IC)
 16 kbytes, 2-way set associative
 256 entries/way, 32-byte block length
 Cache-double-mode (16-kbyte cache)
 Index mode
 SH7750/SH7750S-compatible mode (8 kbytes, direct mapping)
• Operand cache (OC)
 32 kbytes, 2-way set associative
 512 entries/way, 32-byte block length
 Cache-double-mode (32-kbyte cache)
 Index mode
 RAM mode (16-kbyte cache + 16-kbyte RAM)
 SH7750/SH7750S-compatible mode (16 kbytes, direct mapping)
• Single-stage copy-back buffer, single-stage write-through buffer
• Cache memory contents can be accessed directly by address mapping
(usable as on-chip memory)
• Store queue (32 bytes × 2 entries)
Rev. 6.0, 07/02, page 5 of 986