HD6417750 Datasheet, PDF (813/1039 Pages) Renesas Technology Corp – SuperH RISC engine

H-UDI: Hitachi use debug interface
GPIOI: I/O port interrupt
DMTE0–DMTE7: DMAC transfer end interrupts
DMAE: DMAC address error interrupt
*1 Interrupt priority levels can only be changed in the SH7750S or SH7750R. In the
SH7750, the initial values cannot be changed.
*2 SH7750R only
19.3 Register Descriptions
19.3.1 Interrupt Priority Registers A to D (IPRA–IPRD)
Interrupt priority registers A to D (IPRA–IPRD) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for on-chip peripheral module interrupts. IPRA to IPRC are initialized
to H'0000 and IPRD is to H'DA74 by a reset. They are not initialized in standby mode.
IPRA to IPRC
Bit: 15
14
13
12
11
10
9
8
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IPRD (SH7750S and SH7750R only)
Bit: 15
14
13
12
11
10
9
8
Initial value:
1
1
0
1
1
0
1
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
Initial value:
0
1
1
1
0
1
0
0
R/W: R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 6.0, 07/02, page 761 of 986