HD6417750 Datasheet, PDF (479/1039 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
Bank
Precharge-sel
Address
Tncp Tnop Tc1 Tc2 Tc3 Tc4 Trw1 Trw1
Row
H/L
c1
RD/
DQMn
D63–D0
(read)
c1
c2
c3
c4
CKE
Single-address DMA
DACKn
(SA: IO → memory)
Normal write
Note: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as
shown by the solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal
is output as shown by the dotted line. DACKn shows an example where DMAC, CHCRn,
and AL (acknowledge level) are 0.
Figure 13.36 Burst Write Timing (Same Row Address)
Rev. 6.0, 07/02, page 427 of 986