HD6417750 Datasheet, PDF (351/1039 Pages) Renesas Technology Corp – SuperH RISC engine

input clock is the external clock (TCLK) or internal clock (Pφ), TCNT contents are retained in
standby mode.
12.2.6 Timer Control Registers (TCR)
The TCR registers are 16-bit readable/writable registers. There are five TCR registers, one for
each channel.
Each TCR selects the count clock, specifies the edge when an external clock is selected in
channels 0 to 2, and controls interrupt generation when the flag indicating timer counter (TCNT)
underflow is set to 1. TCR2 is also used for channel 2 input capture control, and control of
interrupt generation in the event of input capture.
The TCR registers for channels 0 to 2 are initialized to H'0000 by a power-on or manual reset, but
are not initialized and retain their contents in standby mode. The TCR registers for channels 3 and
4 of the SH7750R are initialized to H'0000 by a power-on reset, but are not initialized and retain
their contents on a manual reset and in standby mode.
1. Channel 0 and 1 TCR bit configuration
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
UNF
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 7
—
Initial value: 0
R/W: R
6
5
4
3
2
1
0
—
UNIE CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Rev. 6.0, 07/02, page 299 of 986