HD6417750 Datasheet, PDF (579/1039 Pages) Renesas Technology Corp – SuperH RISC engine

CPU
DMAC CH1 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH0 DMAC CH1 DMAC CH1
CH0
CH1
CH0
CPU
CPU
DMAC channel 1
burst mode
DMAC channel 0 and
channel 1 round robin
mode
DMAC channel 1
burst mode
CPU
Priority system: Round robin mode
Channel 0:
Cycle steal mode
Channel 1:
Burst mode (edge-sensing)
Figure 14.11 Bus Handling with Two DMAC Channels Operating
Note: When channel 1 is in level-sensing burst mode with the settings shown in figure 14.11, the
bus is passed to the CPU during a break in requests.
14.3.5 Number of Bus Cycle States and '5(4 Pin Sampling Timing
Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the
bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus
master. See section 13, Bus State Controller (BSC), for details.
'5(4 Pin Sampling Timing: In external request mode, the '5(4 pin is sampled at the rising
edge of CKIO clock pulses. When '5(4 input is detected, a DMAC bus cycle is generated and
DMA transfer executed after four CKIO cycles at the earliest.
The second and subsequent '5(4 sampling operations are performed one cycle after the start of
the first DMAC transfer bus cycle (in the case of single address mode).
DRAK is output for one cycle only, once each time '5(4 is detected, regardless of the transfer
mode or '5(4 detection method. In the case of burst mode edge detection, '5(4 is sampled in
the first cycle only, and so DRAK is output in the first cycle only .
Operation: Figures 14.12 to 14.22 show the timing in each mode.
1. Cycle Steal Mode
In cycle steal mode, The '5(4 sampling timing differs for dual address mode and single
address mode, and for level detection and edge detection of '5(4.
For example, in figure 14.12 (cycle steal mode, dual address mode, level detection), DMAC
transfer begins, at the earliest, four CKIO cycles after the first sampling operation. The second
sampling operation is performed one cycle after the start of the first DMAC transfer write
cycle. If '5(4 is not detected at this time, sampling is executed in every subsequent cycle.
Rev. 6.0, 07/02, page 527 of 986