HD6417750 Datasheet, PDF (47/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Figure 22.49 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS[2:0] = 000, TRC[2:0] = 001) ............................................................... 912
Figure 22.50 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
(TRAS[2:0] = 001, TRC[2:0] = 001) ............................................................... 913
Figure 22.51 DRAM Bus Cycle: DRAM Self-Refresh (TRC[2:0] = 001) ............................ 914
Figure 22.52 PCMCIA Memory Bus Cycle
(1) TED[2:0] = 000, TEH[2:0] = 000, No Wait
(2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait +
One External Wait............................................................................................ 915
Figure 22.53 PCMCIA I/O Bus Cycle
(1) TED[2:0] = 000, TEH[2:0] = 000, No Wait
(2) TED[2:0] = 001, TEH[2:0] = 001, One Internal Wait +
One External Wait............................................................................................ 916
Figure 22.54 PCMCIA I/O Bus Cycle (TED[2:0] = 001, TEH[2:0] = 001,
One Internal Wait, Bus Sizing) ........................................................................ 917
Figure 22.55 MPX Basic Bus Cycle: Read
(1) 1st Data (One Internal Wait)
(2) 1st Data (One Internal Wait + One External Wait)..................................... 918
Figure 22.56 MPX Basic Bus Cycle: Write
(1) 1st Data (No Wait)
(2) 1st Data (One Internal Wait)
(3) 1st Data (One Internal Wait + One External Wait)..................................... 919
Figure 22.57 MPX Bus Cycle: Burst Read
(1) 1st Data (One Internal Wait), 2nd to 8th Data (One Internal Wait)
(2) 1st Data (One Internal Wait), 2nd to 4th Data (One Internal Wait +
One External Wait)........................................................................................... 920
Figure 22.58 MPX Bus Cycle: Burst Write
(1) No Internal Wait
(2) 1st Data (One Internal Wait), 2nd to 4th Data (No Internal Wait +
External Wait Control) ..................................................................................... 921
Figure 22.59 Memory Byte Control SRAM Bus Cycles
(1) Basic Read Cycle (No Wait)
(2) Basic Read Cycle (One Internal Wait)
(3) Basic Read Cycle (One Internal Wait + One External Wait)...................... 922
Figure 22.60 Memory Byte Control SRAM Bus Cycle: Basic Read Cycle
(No Wait, Address Setup/Hold Time Insertion, AnS[0] = 1, AnH[1:0] =01) .. 923
Figure 22.61 TCLK Input Timing ......................................................................................... 930
Figure 22.62 RTC Oscillation Settling Time at Power-On.................................................... 930
Figure 22.63 SCK Input Clock Timing ................................................................................. 930
Figure 22.64 SCI I/O Synchronous Mode Clock Timing ...................................................... 931
Figure 22.65 I/O Port Input/Output Timing........................................................................... 931
Figure 22.66(a) '5(4/DRAK Timing...................................................................................... 931
Figure 22.66(b) '%5(4/75 Input Timing and %$9/ Output Timing..................................... 932
Rev. 6.0, 07/02, page xlv of I