HD6417750 Datasheet, PDF (946/1039 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
BANK
Precharge-sel
Address
RD/
Tnop
(Tnop)
Tc1
Tc2
Tc3
Tc4
Trwl
Trwl
t_AD
Row
H/L
c0
t_CSD
t_RWD
t_RWD
t_AD
t_CSD
DQMn
D63–D0
(write)
t_CASD2
t_CASD2
t_WDD
t_DQMD
t_WDD
t_WDD
d0
d1
t_BSD
t_BSD
t_DQMD
d2
d3
CKE
DACKn
(SA: IO → memory)
t_DACD
SA-DMA
Normal write
t_DACD
Notes: In the case of SA-DMA only, the (Tnop) cycle is inserted, and the DACKn signal is output as shown by the
solid line. In a normal write, the (Tnop) cycle is omitted and the DACKn signal is output as shown by the
dotted line.
IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 22.32 Synchronous DRAM Normal Write Bus Cycle: WRITE Command, Burst
(TRWL[2:0] = 010)
Rev. 6.0, 07/02, page 894 of 986