HD6417750 Datasheet, PDF (120/1039 Pages) Renesas Technology Corp – SuperH RISC engine

3.3.3 Virtual Address Space
Setting the MMUCR.AT bit to 1 enables the P0, P3, and U0 areas of the physical memory space in
the SH7750 Series to be mapped onto any external memory space in 1-, 4-, or 64-kbyte, or 1-
Mbyte, page units. By using an 8-bit address space identifier, the P0, U0, P3, and store queue
areas can be increased to a maximum of 256. This is called the virtual memory space. Mapping
from virtual memory space to 29-bit external memory space is carried out using the TLB. Only
when area 7 in external memory space is accessed using virtual memory space, addresses H'1C00
0000 to H'1FFF FFFF of area 7 are not designated as a reserved area, but are equivalent to the P4
area control register area in the physical memory space. Virtual memory space is illustrated in
figure 3.6.
256
P0 area
Cacheable
Address translation possible
External 256
memory space
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
U0 area
Cacheable
Address translation possible
P1 area
Cacheable
Address translation not possible
P2 area
Non-cacheable
Address translation not possible
P3 area
Cacheable
Address translation possible
P4 area
Non-cacheable
Address translation not possible
Privileged mode
Address error
Store queue area
Address error
User mode
Figure 3.6 Virtual Address Space (MMUCR.AT = 1)
In the state of cache enabling, when the areas of P0, P3, and U0 are mapped onto a PCMCIA
interface area by means of the TLB, it is necessary either to specify 1 for the WT bit or to specify
0 for the C bit on that page. At that time, the regions are accessed by the values of SA and TC set
in page units of the TLB.
Rev. 6.0, 07/02, page 68 of 986