HD6417750 Datasheet, PDF (343/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Section 12 Timer Unit (TMU)
12.1 Overview
The SH7750 Series of microprocessors include an on-chip 32-bit timer unit (TMU). The TMU of
the SH7750 or SH7750S has three 32-bit timer channels (channels 0 to 2), and the TMU of the
SH7750R has five channels (channels 0 to 4).
12.1.1 Features
The TMU has the following features.
• Auto-reload type 32-bit down-counter provided for each channel
• Input capture function provided in channel 2
• Selection of rising edge or falling edge as external clock input edge when external clock is
selected or input capture function is used
• 32-bit timer constant register for auto-reload use, readable/writable at any time, and 32-bit
down-counter provided for each channel
• For channels 0 to 2, selection of seven counter input clocks for each channel
External clock (TCLK), on-chip RTC output clock, five internal clocks (Pφ/4, Pφ/16, Pφ/64,
Pφ/256, Pφ/1024) (Pφ is the peripheral module clock)
• For channels 3 and 4, selection is made among five internal clocks (SH7750R only).
• Channels 0 to 2 can also operate in module standby mode when the on-chip RTC output clock
is selected as the counter input clock; that is, timer operation continues even when the clock
has been stopped for the TMU.
Timer count operations using an external or internal clock are only possible when a clock is
supplied to the timer unit.
• Two interrupt sources
One underflow source (each channel) and one input capture source (channel 2)
• DMAC data transfer request capability
On channel 2, a data transfer request is sent to the DMAC when an input capture interrupt is
generated.
Rev. 6.0, 07/02, page 291 of 986