HD6417750 Datasheet, PDF (817/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 19.7 Interrupt Request Sources and the Bits of the INTPRI00 Register
Bit
Register 31 to 28 27 to 24 23 to 20 19 to 16 15 to 12 11 to 8 7 to 4
3 to 0
Interrupt- Reserved
priority-level
setting
register 00
Reserved
Reserved
Reserved
TMU ch4 TMU ch3 Reserved
Reserved
Note:
As shown in the table above, levels for all eight on-chip peripheral modules are assigned in
a single register. The interrupt priority level for the interrupt source that corresponds to each
set of four bits is set as a value from H'F (1111) to H'0 (0000). The setting H'F selects
interrupt priority level 15, which is the highest, and H'0 selects level 0, which means that
interrupt requests from that source are masked.
Reserved bits are always read as 0. When writing, only 0s should be written to these bits.
19.3.4 Interrupt Source Register 00 (INTREQ00) (SH7750R Only)
The interrupt source register 00 (INTREQ00) indicates the origin of the interrupt request that has
been sent to the INTC. The states of the bits in this register is not affected by masking of the
corresponding interrupts by the settings in the INTPRI00 or INTMSK00 register. INTREQ00 is a
32-bit read-only register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit 31 to 0—Interrupt Request: Each of the non-reserved bits in this register indicates that there
is an interrupt request relevant to that bit. For the correspondence between the bits and interrupt
sources, see section 19.3.7, Bit Assignments of INTREQ00, INTMSK00, and INTMSKCLR00
(SH7750R Only).
Bits 31 to 0
0
1
Description
There is no interrupt request that corresponds to this bit
There is an interrupt request that corresponds to this bit.
Rev. 6.0, 07/02, page 765 of 986