HD6417750 Datasheet, PDF (786/1039 Pages) Renesas Technology Corp – SuperH RISC engine

SCI I/O port block diagrams are shown in figures 18.3 to 18.5.
MD0/SCK
Mode setting
register
Reset
R
QD
SPB1IO
C
SPTRW
Reset
QR _D
SPB1DT
C
SPTRW
Internal data bus
SCI
Clock output enable signal
Serial clock output signal _*
Serial clock input signal
Clock input enable signal
SPTRR
SPTRW: Write to SPTR
SPTRR: Read SPTR
Note: * Signals that set the SCK pin function as internal clock output or external clock input according to
the CKE0 and CKE1 bits in SCSCR1 and the C/ bit in SCSMR1.
Figure 18.3 MD0/SCK Pin
Rev. 6.0, 07/02, page 734 of 986