HD6417750 Datasheet, PDF (49/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 7.12 Floating-Point Graphics Acceleration Instructions ............................................ 191
Table 8.1
Instruction Groups.............................................................................................. 200
Table 8.2
Parallel-Executability ......................................................................................... 204
Table 8.3
Execution Cycles................................................................................................ 211
Table 9.1
Status of CPU and Peripheral Modules in Power-Down Modes ........................ 222
Table 9.2
Power-Down Mode Registers ............................................................................ 223
Table 9.3
Power-Down Mode Pins .................................................................................... 223
Table 9.4
State of Registers in Standby Mode ................................................................... 231
Table 10.1 CPG Pins ............................................................................................................ 252
Table 10.2 CPG Register...................................................................................................... 252
Table 10.3 (1) Clock Operating Modes (SH7750, SH7750S).................................................... 253
Table 10.3 (2) Clock Operating Modes (SH7750R) .................................................................. 253
Table 10.4 FRQCR Settings and Internal Clock Frequencies .............................................. 254
Table 10.5 WDT Registers................................................................................................... 260
Table 11.1 RTC Pins ............................................................................................................ 269
Table 11.2 RTC Registers .................................................................................................... 269
Table 11.3 Crystal Oscillator Circuit Constants (Recommended Values) ........................... 289
Table 12.1 TMU Pins ........................................................................................................... 292
Table 12.2 TMU Registers ................................................................................................... 293
Table 12.3 TMU Interrupt Sources ...................................................................................... 309
Table 13.1 BSC Pins ............................................................................................................ 314
Table 13.2 BSC Registers .................................................................................................... 318
Table 13.3 External Memory Space Map............................................................................. 320
Table 13.4 PCMCIA Interface Features............................................................................... 322
Table 13.5 PCMCIA Support Interfaces .............................................................................. 323
Table 13.6 MPX Interface is Selected (Areas 0 to 6) ........................................................... 350
Table 13.7 (1) 64-Bit External Device/Big-Endian Access and Data Alignment ...................... 372
Table 13.7 (2) 64-Bit External Device/Big-Endian Access and Data Alignment ...................... 373
Table 13.8 32-Bit External Device/Big-Endian Access and Data Alignment ...................... 374
Table 13.9 16-Bit External Device/Big-Endian Access and Data Alignment ...................... 375
Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment ........................ 376
Table 13.11 (1) 64-Bit External Device/Little-Endian Access and Data Alignment ................... 377
Table 13.11 (2) 64-Bit External Device/Little-Endian Access and Data Alignment ................... 378
Table 13.12 32-Bit External Device/Little-Endian Access and Data Alignment ................... 379
Table 13.13 16-Bit External Device/Little-Endian Access and Data Alignment ................... 380
Table 13.14 8-Bit External Device/Little-Endian Access and Data Alignment ..................... 381
Table 13.15 Relationship between AMXEXT and AMX2–0 Bits and
Address Multiplexing......................................................................................... 399
Table 13.16 Example of Correspondence between SH7750 Series and Synchronous DRAM
Address Pins (64-Bit Bus Width, AMX2–AMX0 = 011, AMXEXT = 0) ......... 416
Table 13.17 Cycles for which Pipeline Access is Possible .................................................... 431
Table 13.18 Relationship between Address and CE when Using PCMCIA Interface ........... 446
Table 14.1 DMAC Pins ........................................................................................................ 493
Rev. 6.0, 07/02, page xlvii of I