HD6417750 Datasheet, PDF (477/1039 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
Bank
Precharge-sel
Address
Tpr Tpc Tr Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4
Row
Row
H/L
Row
c1
RD/
DQMn
D63–D0
(read)
c1
c2
c3
c4
CKE
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.34 Burst Read Timing (RAS Down, Different Row Addresses)
Rev. 6.0, 07/02, page 425 of 986