HD6417750 Datasheet, PDF (279/1039 Pages) Renesas Technology Corp – SuperH RISC engine

9.2.4 Standby Control Register 2 (STBCR2)
Standby control register 2 (STBCR2) is an 8-bit readable/writable register that specifies the sleep
mode and deep sleep mode transition conditions. It is initialized to H'00 by a power-on reset via
the 5(6(7 pin or due to watchdog timer overflow.
Bit: 7
6
5
4
3
2
1
0
DSLP STHZ*² —
—
—
— MSTP6*¹ MSTP5*¹
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W
R
R
R
R
R/W R/W
Notes: *1 Reserved bit in the SH7750.
*2 Reserved bit in the SH7750 and SH7750S.
Bit 7—Deep Sleep (DSLP): Specifies a transition to deep sleep mode
Bit 7: DSLP
Description
0
Transition to sleep mode or standby mode on execution of SLEEP
instruction, according to setting of STBY bit in STBCR register (Initial value)
1
Transition to deep sleep mode on execution of SLEEP instruction*
Note: * When the STBY bit in the STBCR register is 0
Bit 6 (SH7750R Only)—STATUS Pin High-Impedance Control (STHZ): This bit selects
whether the STATUS0 and 1 pins are set to high-impedance when in hardware standby mode.
Bit 6: STHZ
0
1
Description
Sets STATUS0, 1 pins to high-impedance when in hardware standby mode
(Initial value)
Drives STATUS0, 1 pins to LH when in hardware standby mode
Bit 6 (SH7750 and SH7750S)—Reserved: Only 0 should only be written to these bits; operation
cannot be guaranteed if 1 is written. These bits are always read as 0.
Bits 5 to 2—Reserved: Only 0 should only be written to these bits; operation cannot be
guaranteed if 1 is written. These bits are always read as 0.
Bits 1 and 0 (SH7750)—Reserved: Only 0 should only be written to these bits; operation cannot
be guaranteed if 1 is written. These bits are always read as 0.
Rev. 6.0, 07/02, page 227 of 986