HD6417750 Datasheet, PDF (274/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 9.1 Status of CPU and Peripheral Modules in Power-Down Modes
Status
Power-
Down
Mode
Entering
Conditions CPG
CPU
On-Chip
Memory
On-chip
Peripheral
Modules Pins
External Exiting
Memory Method
Sleep
SLEEP
instruction
executed
while STBY
bit is 0 in
STBCR
Operating Halted
(registers
held)
Held
Operating Held
Refreshing ^{• Interrupt}
• Reset
Deep
sleep
SLEEP
instruction
executed
while STBY
bit is 0 in
STBCR,
and DSLP
bit is 1 in
STBCR2
Operating Halted
(registers
held)
Held
Operating Held
(DMA
halted)
Self-
• Interrupt
refreshing • Reset
Standby
SLEEP
instruction
executed
while STBY
bit is 1 in
STBCR
Halted
Halted Held
(registers
held)
Halted* Held
Self-
• Interrupt
refreshing • Reset
Hardware Setting CA
standby pin low
(SH7750S,
SH7750R)
Halted
Halted
Undefined Halted*
High
Undefined ^{• Power-on}
impedance
reset
Module
standby
Setting
MSTP bit
to 1 in
STBCR/
STBCR2
Operating Operating Held
Specified
modules
halted*
Held
Refreshing ^{• Clearing}
MSTP bit
to 0
• Reset
Note: * The RTC operates when the START bit in RCR2 is 1 (see section 11, Realtime Clock
(RTC)).
Rev. 6.0, 07/02, page 222 of 986