HD6417750 Datasheet, PDF (739/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 16.5 Serial Transmit/Receive Formats
SCSMR2
Settings
CHR PE STOP
Serial Transmit/Receive Format and Frame Length
1 2 3 4 5 6 7 8 9 10 11 12
0 00
S
8-bit data
STOP
0 01
S
8-bit data
STOP STOP
0 10
S
8-bit data
P STOP
0 11
S
8-bit data
P STOP STOP
1 00
S
7-bit data
STOP
1 01
S
7-bit data
STOP STOP
1 10
S
7-bit data
P STOP
1 11
S
S: Start bit
STOP: Stop bit
P: Parity bit
7-bit data
P STOP STOP
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK2 pin can be selected as the SCIF’s serial clock, according to the setting of the CKE1 bit
in SCSCR2. For details of SCIF clock source selection, see table 16.4.
When an external clock is input at the SCK2 pin, the clock frequency should be 16 times the bit
rate used.
Rev. 6.0, 07/02, page 687 of 986