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HD6417750 Datasheet, PDF (921/1039 Pages) Renesas Technology Corp – SuperH RISC engine
Table 22.34 Control Signal Timing (2)
HD6417750
F167
HD6417750
F167I
HD6417750
SF167
HD6417750 HD6417750 HD6417750
SVF133
SF167I
BP200M
HD6417750
VF128
*1
HD6417750
SVBT133
*1
HD6417750
SF200
*2
HD6417750
SBP200
*3
Item
Symbol Min Max Min Max Min Max Min Max Unit Figure
%5(4 setup tBREQS
time
3.5 —
3.5 —
3.5 —
3
— ns 22.13
%5(4 hold
time
tBREQH
1.5 —
1.5 —
1.5 —
1.5 — ns 22.13
%$&. delay tBACKD
time
— 10
— 10
—8
— 6 ns 22.13
Bus tri-state tBOFF1
delay time
— 15
— 15
— 12
— 10 ns 22.13
Bus tri-state
delay time
to standby
mode
tBOFF2
—2
—2
—2
—2
tcyc 22.14
Bus buffer
tBON1
on time
— 15
— 15
— 12
— 10 ns 22.13
Bus buffer
tBON2
on time from
standby
—1
—1
—1
—1
tcyc 22.14
STATUS0/1 tSTD1
delay time
— 11
— 11
—9
— 7 ns 22.14
STATUS0/1 tSTD2
delay time
to standby
—2
—2
—2
—2
tcyc 22.14
Notes:
*1
V = 3.0 to 3.6 V, V = typ. 1.5 V, Ta = –20 to +75°C, C = 30 pF, PLL2 on
DDQ
DD
L
*2 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on
(HD6417750F167, HD6417750SF167, HD6417750SF200)
V = 3.0 to 3.6 V, V = typ. 1.8 V, Ta = –40 to +85°C, C = 30 pF, PLL2 on
DDQ
DD
L
(HD6417750F167I, HD6417750SF167I)
*3 VDDQ = 3.0 to 3.6 V, VDD = typ. 1.8 V, Ta = –20 to +75°C, CL = 30 pF, PLL2 on
Notes
Rev. 6.0, 07/02, page 869 of 986