HD6417750 Datasheet, PDF (445/1039 Pages) Renesas Technology Corp – SuperH RISC engine

CKIO
A25–A0
RD/
D63–D0
(read)
D63–D0
(write)
T1
Tw
T2
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.11 SRAM Interface Wait Timing (Software Wait Only)
Rev. 6.0, 07/02, page 393 of 986