HD6417750 Datasheet, PDF (816/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Bit 7—IRL Pin Mode (IRLM): Specifies whether pins ,5/6–,5/3 are to be used as level-
encoded interrupt requests or as four independent interrupt requests.
Bit 7: IRLM
0
1
Description
,5/ pins used as level-encoded interrupt requests
(Initial value)
,5/ pins used as four independent interrupt requests (level-sense IRQ
mode)
Bits 13 to 10 and 6 to 0—Reserved: These bits are always read as 0, and should only be written
with 0.
19.3.3 Interrupt-Priority-Level Setting Register 00 (INTPRI00) (SH7750R Only)
The interrupt-priority-level setting register 00 (INTPRI00) sets the priority levels (levels 15–0) for
the on-chip peripheral module interrupts. INTPRI00 is a 32-bit readable/writable register. It is
initialized to H'00000000 by a reset, but is not initialized when the device enters standby mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Table 19.7 shows the correspondence between interrupt request sources and the bits in INTPRI00.
Rev. 6.0, 07/02, page 764 of 986