HD6417750 Datasheet, PDF (629/1039 Pages) Renesas Technology Corp – SuperH RISC engine

Table 14.13 Register Configuration
Chan-
nel Name
0
DMA source
address register 0
DMA destination
address register 0
DMA transfer
count register 0
DMA channel
control register 0
1
DMA source
address register 1
DMA destination
address register 1
DMA transfer
count register 1
DMA channel
control register 1
2
DMA source
address register 2
DMA destination
address register 2
DMA transfer
count register 2
DMA channel
control register 2
3
DMA source
address register 3
DMA destination
address register 3
DMA transfer
count register 3
DMA channel
control register 3
Com- DMA operation
mon register
Abbre-
viation
SAR0
Read/
Write
R/W*²
Area 7
Initial Value P4 Address Address
Access
Size
Undefined H'FFA00000 H'1FA00000 32
DAR0
R/W*² Undefined H'FFA00004 H'1FA00004 32
DMATCR0 R/W*² Undefined H'FFA00008 H'1FA00008 32
CHCR0 R/W*¹*² H'00000000 H'FFA0000C H'1FA0000C 32
SAR1
R/W Undefined H'FFA00010 H'1FA00010 32
DAR1
R/W Undefined H'FFA00014 H'1FA00014 32
DMATCR1 R/W Undefined H'FFA00018 H'1FA00018 32
CHCR1 R/W*¹ H'00000000 H'FFA0001C H'1FA0001C 32
SAR2
R/W Undefined H'FFA00020 H'1FA00020 32
DAR2
R/W Undefined H'FFA00024 H'1FA00024 32
DMATCR2 R/W Undefined H'FFA00028 H'1FA00028 32
CHCR2 R/W*¹ H'00000000 H'FFA0002C H'1FA0002C 32
SAR3
R/W Undefined H'FFA00030 H'1FA00030 32
DAR3
R/W Undefined H'FFA00034 H'1FA00034 32
DMATCR3 R/W Undefined H'FFA00038 H'1FA00038 32
CHCR3 R/W*¹ H'00000000 H'FFA0003C H'1FA0003C 32
DMAOR R/W*¹ H'00000000 H'FFA00040 H'1FA00040 32
Rev. 6.0, 07/02, page 577 of 986