HD6417750 Datasheet, PDF (855/1039 Pages) Renesas Technology Corp – SuperH RISC engine

21.2 Register Descriptions
21.2.1 Instruction Register (SDIR)
The instruction register (SDIR) is a 16-bit register that can only be read by the CPU. In the initial
state, bypass mode is set. The value (command) is set from the serial input pin (TDI). SDIR is
initialized by the 7567 pin or in the TAP Test-Logic-Reset state. When this register is written to
from the H-UDI, writing is possible regardless of the CPU mode. However, if a read is performed
by the CPU while writing is in progress, it may not be possible to read the correct value. In this
case, SDIR should be read twice, and then read again if the read values do not match. Operation is
undefined if a reserved command is set in this register.
SH7750, SH7750S:
Bit: 15
14
13
12
11
10
9
8
TI3
TI2
TI1
TI0
—
—
—
—
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R
R
R
R
R
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R
R
R
R
R
Bits 15 to 12—Test Instruction Bits (TI3–TI0)
Bit 15: TI3
0
1
Bit 14: TI2
0
1
0
1
Bit 13: TI1
—
0
1
0
1
0
1
Bit 12: TI0
—
—
0
1
—
—
—
0
1
Description
Reserved
Reserved
H-UDI reset negate
H-UDI reset assert
Reserved
H-UDI interrupt
Reserved
Reserved
Bypass mode
(Initial value)
Bits 11 to 0—Reserved: These bits are always read as 1, and should only be written with 1.
Rev. 6.0, 07/02, page 803 of 986